EDA software tools may be used in the design and analysis of numerous electronic systems such as printed circuit boards (PCBs) and integrated circuits (ICs). To design a circuit, such as an integrated circuit (IC), a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language (HDL). Common examples of HDLs include Verilog and VHDL. An EDA system typically receives the high level behavioral descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction. Essentially, the process to implement an electronic device begins with functional design and verification (e.g., using RTL), and then proceeds to physical design of a layout and verification.
Circuit designers and verification engineers use different methods to verify circuit designs. One common method of verification is the use of simulation. Simulation dynamically verifies a design by monitoring behaviors of the design with respect to test stimuli. For many types of designs, simulation can and should be performed during the design process to ensure that the ultimate goals are achievable and will be realized by the finished product.
For example, SPICE and FASTSPICE are common types of simulators that perform simulation to verify the operation of an electronic design. With these types of tools, the electronic design is converted into a system of equation(s), which is then solved for a given set of inputs to check the state of specific portions of the circuit at given points in time.
Some EDA tools are configured to handle the issue of electro static discharge (“ESD”). ESD generally relates to the transfer of charge between bodies at different electrical potentials. However, electrostatic discharge may alter the electrical characteristics of a semiconductor device, which may degrade or destroy the device. Since ESD is a high surge current relative to those for otherwise normal operation of the device, EDS events can cause major reliability problems in integrated circuits and for the semiconductor industry. Furthermore, ESD may also be a cause of oxide damage in integrated circuits.
In order to protect the functional modules in integrated circuits from ESD events, protection cells are often utilized between the functional modules and the input/output (“I/O”) terminals (e.g., bumps, pins, pads, etc.) of the integrated circuit. For example, for ESD protection it is often required that for each bump in the electrical circuit there exists an ESD cell through which its static charge can be discharged without damaging the device. To ensure that static charge on a bump is discharged only through the bump of the device, it is necessary to ensure that the effective electrical resistance of the bump is below an identified threshold so that the static charge does not go through any other device. In order to ensure this, a large number of effective electrical resistances need to be calculated from multiple sources to multiple destinations.
Furthermore, it has been seen that the current caused by ESD events can be so large that the current gets uniformly distributed on a net before it gets drained out. Meanwhile, even when the bumps of the devices behave as expected, there could be large voltage drops across driver and receiver pairs due to a large current flowing and a high resistance between the driver and receiver pairs, which could be the new cause of oxide damage. Therefore, what is needed is an efficient way to simulate the multiple drainage/sink nodes and identify all driver-receiver pairs with differential voltages above a given threshold. Finally, this need is aggravated by the sheer size of the circuits that need simulating.